chikaofili
Junior Member level 3
Hello,
I am trying to perform 3x3 kernel image convolution by using 2 FIFO and 3 shift registers so that I can implement a pipelined fifo
I will prefer not to use the FIFO ipcore in Altera but I dont know how the dual port ram can be used as an FIFO.
I guess my question is ' can someone explain how the read and write address works in dual port ram for FIFO.
Thank u
I am trying to perform 3x3 kernel image convolution by using 2 FIFO and 3 shift registers so that I can implement a pipelined fifo
I will prefer not to use the FIFO ipcore in Altera but I dont know how the dual port ram can be used as an FIFO.
I guess my question is ' can someone explain how the read and write address works in dual port ram for FIFO.
Thank u