At one time I had to do a lot of this, and we found the best
way was to use external scripts (I started with sed -e, then
a CAD lady turned it into cleaner perl scripts for ut) to add
veriloga header, massage vectors (we had timestamp and
value, not just value - you need to assign that somehow)
and veriloga footer, stuff that to underneath a "testVectors"
symbol/veriloga pair as its verilog.va view, and badda-bing,
a pattern generator for schematic based mixed signal.