kelvin_sg
Advanced Member level 4
on"?
because while I am simulating part of a large designs some data files
can be ignored.. However there are statements which can not be get
pass by the simulator. I can set en_read to be negative..
In Verilog ncsim give warnings and continue with the rest..
but I get File I/O error in ncvhdl..
because while I am simulating part of a large designs some data files
can be ignored.. However there are statements which can not be get
pass by the simulator. I can set en_read to be negative..
In Verilog ncsim give warnings and continue with the rest..
but I get File I/O error in ncvhdl..
Code:
if rst = '0' then
file_open(fp, string'())......
else
if (en_read) then
read fp ...
end if