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# How do I calculate (or find out) the output impedance of a logic level output pin?

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#### swen_s

##### Member level 1
How do I calculate (or find out) the output impedance of a logic level output pin?

I read in a book that the impedance can be different when high or low but they didn't show how to calculate the impedance.

Logic outputs are essentially non-linear. If you refer to CMOS outputs, it's usually reasonable to determine the dV/dI slope near the high and low level as a small-signal impedance value when determining optimal transmission line matching. You should be aware that the slow and fast technology edges are apart impedance-wise at least by a factor of two. If your chip is characterized with ISIS files (they exist e.g. for most FPGAs), you can read the minimum, maximum and typical impedance numbers from the output characteristic.

If you don't have clear data for the chip, it's probably the best to determine it be a DC measurement.

Read the description of the logic family, they should provide the information with their logic family. I can't speak for the latest logic as I am out of the field for 7 years. But ECL, LVCMOS, TTL and even 3.3V FPGAs are very low impedance, you don't do impedance matching to the output ( source). You terminate at the load end to the characteristic impedance.

I do know there is a bus system in computers that the data bus drivers are designed to have output impedance like 50ohms. The reason they do this is to save power and relax the drive requirement. The theory behind this is they specified to have OPEN termination at the load, the wave front hits the end of the tx line, then bounce back at almost twice the voltage. But the when the reflected wave reach back to the output of the driver, it sees the 50 ohm termination and the reflection dies. So the data bus always see a round trip reflection, but guaranty it will settle in one round trip time. The clock should sample the data ONLY after one round trip time. You save a lot of power as the data bus driver don't need to drive low impedance. The only signal that require high current drive is the clock line.

Impedance is more or less not important, but the capasaty to drive other inputs is important. This fan out changes when selecting different input devices, where type - type normaly has the largest fan out. Examble :
HCT - HCT fan out against HCT - ALS
But if i was doing a strong constraint design i would rely more on simulations based on vendor libraries. And not my calculator .

Look up IBIS information for the device, SIV (signal integrity verification) software uses this information, you also get drive capability etc. this info is used within the SIV package and generally you dont need to know it in isolation.

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