How do floorplan and placement affect timing of a design

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microe_victor

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do the EDA tools change the netlist during floorplan and placement to meet the timing requirement ? or just adjust the position of the cells?

if we adjust the position of the cell, what is changed by doing this except the wire and all timing information related to the wire?

what can we do in Physical Synthesis?

thanks
 

In our backend design flow (EDA tools is ASTRO), ASTRO do change netlist during floorplan and placement by sizing cells or adding, removing, sizing buffer to meet timing requirements (to meet setup or hold time). not just adjust the position of the cells.

 

thank you for your help

I have another question
we estimate the aera of a block and then use wire load mode accordingly to calculate the timing at pre-layout stage
then after placement ,the detail routing has not been done
how do we calculate the wire load delay ?
it is said that we extract parasitical RC from the model
then what kind of model we are extracting from without a detailed routing information


 

if u place timing criticl blocks far , than ur timing got worse.
 

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