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You could create a setup where one a clock signal is flopped using any other async clock. This will cause a good number of metastability cases. Then, flop the output of that flop into two flops -- one with the same clock as the metastable flop, and one with a variable delay attached to the same clock.
Put a comparator between the two flops, and count the number of times they are not the same. Put the variable delay to a high enough number to have no miscompares, and then start lowering it until you do see them appearing. That'll give you a good idea of the longest time your flop is staying metastable.
You could create a setup where one a clock signal is flopped using any other async clock. This will cause a good number of metastability cases. Then, flop the output of that flop into two flops -- one with the same clock as the metastable flop, and one with a variable delay attached to the same clock.
Put a comparator between the two flops, and count the number of times they are not the same. Put the variable delay to a high enough number to have no miscompares, and then start lowering it until you do see them appearing. That'll give you a good idea of the longest time your flop is staying metastable.
Many thanks for your feasible guideline. I'm little confusing with your statement "and then start lowering it until you do see them appearing". I don't exactly catch your points. If it's convenient to you, could you elaborate it? Do you mean to reduce the number of setup violations by enlarging margins of timing discrepancy between data and clock?
Well, I would say it wont be possible to accurately measure it economically, or may be I dont know how to do it. But pls pls let me know why do you want to measure it.
Kr,
Avi http://www.vlsiip.com
Understand the purpose of "detect the metastable" and "design to avoid the metastable" but dont know the reason of "measure metastability". pls share ur purpose. Is ur design that could accept the metastability in some degree?
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