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how can i use another multiply algorithm in my code?

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fahim1

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hi
i wrote anthor code for multiply algorithm and i want to use it instead of * that is defined in my vhdl code,
how could i do this to be synthesizable???
 

fahim1

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:grin:
it is not completed so i cant put it here :) but assume there is a code for booth multiply algorithm and and i have this line in my main code
Code:
prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0);
i want to use booth multiply algorithm istead of *.
 

dpaul

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There are two ways in which you can use it!
Easiest way would be to use it as a function or you can also use it as a separate entity and use it in your top-module.
 
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fahim1

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There are two ways in which you can use it!
Easiest way would be to use it as a function or you can also use it as a separate entity and use it in your top-module.
you mean i put it as a function in apackage then add package.and if the name of entity of algorithm is booth
i should write it what instead of * ??
Code:
prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0);
 

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The mulf_fn() function can be the substitute for the "coef(1)*reg(2)" part. The fn. can take 2 inputs and generate/return the product as its output.

So your code can look like-
prod := mult_fn(...) + mult_fn(...) + mult_fn(...);
 
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TrickyDicky

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You can do it by a function if you want, but it wont have any pipelining, so the fmax will be very slow. You'll need to do an entity instantiation for that.
Why do you want to use booth over * (which will us the fast build in multipliers) anyway?
 

fahim1

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You can do it by a function if you want, but it wont have any pipelining, so the fmax will be very slow. You'll need to do an entity instantiation for that.
Why do you want to use booth over * (which will us the fast build in multipliers) anyway?
i want to implenet a low power fir filter and modified booth making traditional multipliers lowpower according to decreasing partial products
 

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i want to implenet a low power fir filter and modified booth making traditional multipliers lowpower according to decreasing partial products
I highly doubt that creating a multiplier in an FPGA LUT fabric will use less power than the hard IP macro for DSP that is in many FPGA families. There's a reason FPGA vendors "waste" silicon area for DSP macros, i.e.: less power, higher performance, and less area.
 

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