xrisas1
Newbie level 3
import system verilog
Hi Guys,
I need to import a VHDL package into a SystemVerilog Envirnment. Does Anybody know how this can be done?
import package::*
and
`include "package.vhd"
and
instantiating the package as a unit in the sv file
DO NOT WORK
Thanks
Hi Guys,
I need to import a VHDL package into a SystemVerilog Envirnment. Does Anybody know how this can be done?
import package::*
and
`include "package.vhd"
and
instantiating the package as a unit in the sv file
DO NOT WORK
Thanks