Could any one help me out in this problem..............
Here is the problem...........
I am having a Verilog desing having 5 modules ...instantiated one inside the other.
Now If I want to identify all the paths from the top module to the bottom module how can I do that using Xilinx ISE 8.1i
Note : The Identification of path is not going to be have any constraints..
Thanx for the suggestion,
But looking into the rtl viewer will give me just 7-8 pages of gates...
and i might end up with having paths ....that can also me only false one.
If u have done that through rtl viewer then tell me the exact way towards the approach to solve such a problem