Jyotshna_Sharma
Newbie level 4
Could any one help me out in this problem..............
Here is the problem...........
I am having a Verilog desing having 5 modules ...instantiated one inside the other.
Now If I want to identify all the paths from the top module to the bottom module how can I do that using Xilinx ISE 8.1i
Note : The Identification of path is not going to be have any constraints..
Here is the problem...........
I am having a Verilog desing having 5 modules ...instantiated one inside the other.
Now If I want to identify all the paths from the top module to the bottom module how can I do that using Xilinx ISE 8.1i
Note : The Identification of path is not going to be have any constraints..