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How can I find all the negedge trigged flip-flops.

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wkong_zhu

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How can i find all the negedge trigged flip-flops in the entire design.

Can I use synopsys to achieve it?
Or other tools?
 

cedance

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truly, i couldnt understand ur question.. u mean u wanted to find all neg. edge triggered flipflops from a source code? or from a synthesised circuit? or what ? am i atleast near ur question?

/Am
 

tukken

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you could find it in rtl code or netlist
 

diablo1222

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Yes, you can use the design compiler. After read the desig and map, you can generate the report.
 

wkong_zhu

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I mean that, The RTL code is not writen by me, but I will do synthesis, P&R, I want to set timing constrants on it, especially the negedge clock flip-flops make trouble, I want to find them all, then do analyze.
 

logicdrag

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Not depend on EDA tools!
you can write a script to check this issue.
 

eziggurat

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I thought it was bad practice to use negative edge triggered flip-flops on a design.
 

pandora

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tukken said:
you could find it in rtl code or netlist
put design to netlist
u could find it in netlist
 

spauls

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DC will put invertor in clock for neg edge F/F
 

niuniu

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just us 'grep' to fine the neg dff in verilog netlist.
 

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