How can I find all the negedge trigged flip-flops.

[wkong_zhu]

How can i find all the negedge trigged flip-flops in the entire design.

Can I use synopsys to achieve it?
Or other tools?

 

[cedance]

truly, i couldnt understand ur question.. u mean u wanted to find all neg. edge triggered flipflops from a source code? or from a synthesised circuit? or what ? am i atleast near ur question?

/Am

 

[tukken]

you could find it in rtl code or netlist

 

[diablo1222]

Yes, you can use the design compiler. After read the desig and map, you can generate the report.

 

[wkong_zhu]

I mean that, The RTL code is not writen by me, but I will do synthesis, P&R, I want to set timing constrants on it, especially the negedge clock flip-flops make trouble, I want to find them all, then do analyze.

 

[logicdrag]

Not depend on EDA tools!
you can write a script to check this issue.

 

[eziggurat]

I thought it was bad practice to use negative edge triggered flip-flops on a design.

 

[pandora]

you could find it in rtl code or netlist

put design to netlist
u could find it in netlist

 

[spauls]

DC will put invertor in clock for neg edge F/F

 

[niuniu]

just us 'grep' to fine the neg dff in verilog netlist.