how can I design SPI slaver by verilog

[well]

I want to write spi slaver module which can be synthesized, but the asynchronous clock domain, I have write a spi slaver module already, but spi clock can't be fast or slow, the module can be use, but is not perfecte! somebody can help me ! thanks!

 

[yibai]

there are many methods to sync the data.
i think you must have another clock to do async interface. so:
1. FIFO
2. just internal Clock to SYNC all the signals.
3. spi clock latch the data, and then do async.
...