how can i call a module from case or if else statement?

[SantoshSoundararajan]

how can i call a module from case or if else statement in verilog?

i need to make a module instantiation whenever particular condition occurs...can someone make me clear on designing control unit like that?

 

[syedshan]

Dear Santosh,

You cannot call a module with conditional statement in HDL. A MODULE IS ESSENTIALLY A HARDWARE, YOU ARE ABOUT TO INTRODUCE IN YOUR DESIGN.

As you know that HDL works as a hardware description language, while the usual software languages (like c)
they can call some function based of different conditions since they run either sequentially or memory is allocated/deallocated
at run-time since they are SOFTWARE and later processor keep track of it.

Where as in HDL design module is different from function, think of it as a sepearate CHIP or IC that you have bought and want
to introduce in your circuit. You have to introduce connect it in any case with you design.
Now what you can do is use some Chip_Enable pin-sort-of-something to enable or dissable that module and its function based on your requirement.


Hope this helps,
bests,
Shan

 

[TrickyDicky]

are we talking VHDL or verilog.

Either way, you cant do what you're asking. Its like making a circuit that adds/removes a chip from the board if the voltage goes above a certain level. Wouldnt you say that was impossible.

 

[SantoshSoundararajan]

Thanks syedshan...can you explain me with some example?
i tried this program and it is showing wrong results...
module arithmetic(A,B,S,out);
input A,B;
input [1:0] S;
output out;
wire en1,en2,en3,en4;

assign en1=(~S[0])&(~S[1]);
assign en2=(S[0])&(~S[1]);
assign en3=(~S[0])&(S[1]);
assign en4=S[1]&S[0];

and1 a1(A,B,en1,out);
or1 o1(A,B,en2,out);
xor1 x1(A,B,en3,out);
nor1 n1(A,B,en4,out);

endmodule


module and1(A,B,en1,out);
input A,B,en1;
output out;
wire out;
assign out=A&B&en1;
endmodule

module or1(A,B,en2,out);
input A,B,en2;
output out;
wire out;
assign out=(A|B)&en2;
//always@(A or B or en2)
// begin
// if(en2)
// out=A|B;
// end
endmodule


module xor1(A,B,en3,out);
input A,B,en3;
output out;
wire out;
assign out=(A^B)&en3;
endmodule


module nor1(A,B,en4,out);
input A,B,en4;
output out;
wire out;
assign out=(~(A|B))&en4;
endmodule

 

[TrickyDicky]

have you simulated the design?
ANd where is the testbench?

 

[SantoshSoundararajan]

here is the test bench

module arith_test;
reg A,B;
reg [1:0] S;
wire out;
arithmetic aaa1(A,B,S,out);
initial
begin
A=0; B=1; S=2'b00;
#100 A=0; B=1; S=2'b01;
#100 A=0; B=1; S=2'b10;
#100 A=0; B=1; S=2'b11;
end
endmodule

 

[TrickyDicky]

then you'e got all you need to debug it. WHats the problem?

 

[SantoshSoundararajan]

i could not get the correct result when i run the program...my aim is when en1 is 1 and module should work and when en2=1 or module should work and so on...

 

[TrickyDicky]

This is the part where you debug the design using the simulation to find out why its not working....

 

[rberek]

Hint. You've wired together the outputs of 4 combinatorial blocks. I would start my debugging there.

r.b.