How can 2 hosts running different clocks write to the same register?

[snoop911]

I'm new to verilog/digital design, so not sure how this is usually
done..

I need to write to a register from 2 sources.. in this case, a pci host
and a microcontroller

Since the clock domains are all different, I can't just have multiple
processes writing to the same register..

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Code Verilog - [expand]
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always @(posedge pciclk or negedge nrst)
   if pci_wr & pci_addr == 0
        cntl_reg = pci_data
 
always @(posedge mcclk or negedge nrst)
   if mc_wr & mc_addr == 0
        cntl_reg = mc_data

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How is this typically done?

 

[KlausST]

Hi,

From the idea usually it makes no sense when two hosts writing data to a register at the same time.
One can never rely on the data in the register.
But on the other hand there are dual port rams made for this..

Therefore usually the two hosts communicate with each other (this can be done with two wires or two bytes) who has writing acces to some dual port ram area.
Often there are three areas used with rotating function...but thats not your question....

To answer your question.
If you are designing a dual port ram, then you may use the one host's clock, the second host's clock or any other clock.
It is not important what you use, because the data has to be considered as "invalid" as long as writing timing is not communicated with the two hosts.

Klaus

 

[FvM]

To trigger dual port RAM inference (with design tools that support it), you need to describe a memory array. In so far the shown code will rather cause a trivial "multiple source" error than synthesizing hardware.

It's because usual hardware registers only have a single clock port.

How is this typically done?

As a first step you have to decide the intended behaviour in case of concurrent accesses. Then determine in which clock domain(s) the register content has to be read.

Some kind of domain crossing technique will be used in most cases. E.g. register locking with synchronized handshake signals or domain crossing FIFO.

 

[K-J]

I'm new to verilog/digital design, so not sure how this is usually
done..

I need to write to a register from 2 sources.. in this case, a pci host
and a microcontroller

Since the clock domains are all different, I can't just have multiple
processes writing to the same register..
How is this typically done?

You will need to arbitrate between the two sources. Since one source is PCI which does have a signal to insert wait states, I would choose that one as the one that has to wait if the two sources are trying to simultaneously access. The basic approach I would suggest:
- Translate your PCI interface into something that is synchronous to the clock that you will be using to actually clock the register. The 'register side' interface then would consist of outputs 'pci_write', 'pci_write_data' and an input called 'pci_wait_request'.
- Do the same thing for the microcontroller interface. Since you didn't specify, I don't really know if that interface can have wait states inserted or not. It doesn't much matter if it can't since your arbiter will be choosing the micro in case of simultaneous access. The 'register side' interface signals here would be 'micro_write', 'micro_write_data'
- Now you create a simple 2 interface arbiter. If 'micro_write' is active, then write to the register with 'micro_write_data'. If not, then if 'pci_write' is active, write to the register with 'pci_write_data'. If both are active, then write to the register with 'micro_write_data' and set 'pci_wait_request' true.

The first two steps move you into a single clock domain so that you can write to the register. The third step allows multiple sources to update the register.

Kevin Jennings