3wais
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How are the chips organized on a typical DDR3 memory module used in PCs ??
I'm not asking about the organization of rows and columns inside memory chips, I'm asking about the connections between these chips and the bus. Do they share the same bus (while each has a 4,8 or 16 data width)?? or is the bus divided somehow to access multiple chips at once?? in cases where more than one memory modules are used (2 or 3 typically) do they also use the same bus??
I have also seen processors that use more than one memory controllers(If I understood that right), how does that apply to DDR3 modules ??
I'm not asking about the organization of rows and columns inside memory chips, I'm asking about the connections between these chips and the bus. Do they share the same bus (while each has a 4,8 or 16 data width)?? or is the bus divided somehow to access multiple chips at once?? in cases where more than one memory modules are used (2 or 3 typically) do they also use the same bus??
I have also seen processors that use more than one memory controllers(If I understood that right), how does that apply to DDR3 modules ??
