mohamedabouzied
Member level 3
pll control
Hello, All
i have deisgned a pll as a frequency synthesizer
i designed the loop filter using matlab using S domain.
All blocks, Charge pump pfd, vco and divider are done in transistor level
when i simulate them all in feedback loop, using transient analysis in cadence
the curve of voltage control has a strange behaviour.
first, it goes as any control system and has a good overshoot
then, its value decreases, which is a good sign
but a fter a while, it starts to rise again digging its way to Vdd unfortunately.
why this last rise a ppear?
what is a poosible problem in my desing?
thanx in advance
MohamedAbouzied
Hello, All
i have deisgned a pll as a frequency synthesizer
i designed the loop filter using matlab using S domain.
All blocks, Charge pump pfd, vco and divider are done in transistor level
when i simulate them all in feedback loop, using transient analysis in cadence
the curve of voltage control has a strange behaviour.
first, it goes as any control system and has a good overshoot
then, its value decreases, which is a good sign
but a fter a while, it starts to rise again digging its way to Vdd unfortunately.
why this last rise a ppear?
what is a poosible problem in my desing?
thanx in advance
MohamedAbouzied