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[hlp] PLL control voltage tends to Vdd

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mohamedabouzied

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pll control

Hello, All
i have deisgned a pll as a frequency synthesizer
i designed the loop filter using matlab using S domain.

All blocks, Charge pump pfd, vco and divider are done in transistor level

when i simulate them all in feedback loop, using transient analysis in cadence

the curve of voltage control has a strange behaviour.

first, it goes as any control system and has a good overshoot
then, its value decreases, which is a good sign
but a fter a while, it starts to rise again digging its way to Vdd unfortunately.

why this last rise a ppear?
what is a poosible problem in my desing?

thanx in advance
MohamedAbouzied
 

pll voltage vdd

If your feedback divider does not work, pll may fail to correct control voltage, and no feedback coming means the vco is not oscillating which moves control voltage to VDD. At the instance of strange behavior please check the output of the feedback divider. Regards.
 
Hi,

schematic r atleast netlst will b much helpful to debug

but here r few suggestions in Qs.

1. all u r blocks working as expected separately in transistor level?

2. can u try simulation without VCO to check the functionality of PFD ->CP ->LPF with a test vector??

thnx
 
thanx for your replay both
but my divider delievers a signal to PFD which is near to equal my reference frequency

about the blackuni:
each block worked separetly as you say.
but i don't understannd your 2nd soultion!!!!!

thanx in advance
MohamedAbouzied

Added after 2 minutes:

i use 3rd order filter
here is a plot of what appears:
the green at output of charge pump
the blue at input of VCO
 

try making a large signal behavior model of the pll and then insert each block at a time, if they work fine then insert block pairs (like pfd, CP)
 

Charge-pump might have mismatch in its up and down current networks, or the PFD is not functioning properly for the input phase difference. You may check the outputs of PFD and the charge-pump seperately and together.
 
Hi,

As "smoked" suggested, my second Q is try simulating PFD+CP+ LPF and check the output of LPF.

for this u can use ideal pwl r pulse 2 supply ref. clk and clk to PFD. But make them to reflect u r original scenario.

Also check u r PFD o/p

can u share schematic r netlist for those 3 ??


Thnx
 

Quote: i use 3rd order filter


No zeros ?
Does this mean you have tried to design a 4th order PLL (as the VCO adds one order) ???
 

Hello
Thanx for our guros for great help.

the problem was the simulator itself.
I used liberal mode for transient simulation.
but this is wrong.

I should have used moderate or conservative modes to have locking.
I hope this is helpful for other people.

salam
MohamedAbouzied
 

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