Hii all,I have a small question in my mind.

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cherry_vlsi

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Before pre CTS clock doest'nt exist, right? yehh Ideal clock anyway exist with estimated parasitics with more scope of miscorrelation. But before CTS y do v go for SETUP fixing then??
 

Before CTS, or lets say at the FE level, we just have wire load model to take care of the parastitics and clock is ideal, this situation is optimistic when we compare w.r.t POST CTS situation.

Lets accept that hold and setup are complimentary stuff, each one of them eats up in other's margin.

POST CTS we have to slow down our paths for hold fixing, this will degrade the clock frequency too, thus we need to optimize our design for setup PRE CTS, so that we have margins which can be eaten up during hold fixing.
 

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