High Speed Sample and Hold Circuit !!!

Hello guys ,

I'm student in swiss federal institute of technology in Zurich . I'm very grad tojoinin this forum with all of you .
In this semester, I have a semester thesis : design a high speed sample and hold (SH) circuit. I use T 0.13um CMOS technology ...
For the OTA, that is used in SH circuit, I have tested all topology telesopic cascode, folded cascode, .... and for the most suitable OTA topologies , I choose the folded cascode with Gain boosting and Two stage Opamp . Between those 2 topologies, it is for me really difficult to decide one .
The supplied voltage is very low (1.2 V) , power dissipation should be as small as possible , the sampling rate is 300 MSample/s, load capacitance 2.5 pF ....
Can you advise me for a right choice ?
Thanks a lot ...
Cherio

I would choose the gain boost ct since it's more stable than two stage, or we can say it's easier to make it stable

I would like to use he folded cascode with Gain boosting , because the two stage is not always stable

it's a very challenging task.
1.2v is very low and the sampling rate is too high. so i will prefer to two stage.

I have the idea as like as renwl .. today I have simulated in Cadence . The Two Stage is more difficult to make it stable, but with a trick ( leak compensation) , you can do it easier .
The two stage with the first stage is cascode , will give a high DC gain and the second stage is common Source . The output swing is very good (800mV) ... for folded cascode with Gain-boosting you have 500mV output swing .

Also, i thank you very much for your comment .

please use gain boosted.