Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Noise analysis of sample and hold amplifier

Chinmaye

Full Member level 3
Joined
Jan 18, 2016
Messages
159
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,751
Dear all,
I am trying to simulate .noise in cadence for a flip-around sample and hold circuit. The sampling frequency is 4MHz. I have connected the inputs to common mode. The freq range is from 1 to 2MHz. I see peaking in the noise response at 165KHz. I think I am missing out on something.
Is there anything that I am missing out on?
 

AMS012

Full Member level 4
Joined
Oct 29, 2012
Messages
232
Helped
48
Reputation
98
Reaction score
59
Trophy points
1,308
Location
India
Activity points
2,758
I agree with guntherleet. You should not do acnoise on a circuit that is not time invariant.

Sample and hold falls into the category of what is called Linear Periodically Time Varying (LPTV) circuits, whose steady state depends on the switching frequency. Go through the literature to get more about it.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top