dfrndez
Newbie level 6
pll high speed
Hello,
Any help below would be much appreciated.
I am implementing a PLL (Frequency Synthesizer), the output of the VCO is to be 26 Ghz and the input is 812.5 Mhz. I plan to use a couple of ILFDs and a static divider. I am implementing the following CML logic style static divider in 130nm CMOS and cannot get the frequency to divide by 2 in Cadence.
Also I get the similar response with the ILFD which I don't really understand because it's a simple LC Oscillator that Cadence told me via PSS oscillates at 13 Ghz independently of the VCO input, yet when I add the 26 Ghz input through a capacitor attached to the gate of the bias transistor, Cadence then outputs a 26 Ghz transient instead of 13 Ghz.
I've attached a doc about what I am referring to exactly. Hopefully this concern may resonate with someone here who encountered such issues before.
Thank you,
David
Hello,
Any help below would be much appreciated.
I am implementing a PLL (Frequency Synthesizer), the output of the VCO is to be 26 Ghz and the input is 812.5 Mhz. I plan to use a couple of ILFDs and a static divider. I am implementing the following CML logic style static divider in 130nm CMOS and cannot get the frequency to divide by 2 in Cadence.
Also I get the similar response with the ILFD which I don't really understand because it's a simple LC Oscillator that Cadence told me via PSS oscillates at 13 Ghz independently of the VCO input, yet when I add the 26 Ghz input through a capacitor attached to the gate of the bias transistor, Cadence then outputs a 26 Ghz transient instead of 13 Ghz.
I've attached a doc about what I am referring to exactly. Hopefully this concern may resonate with someone here who encountered such issues before.
Thank you,
David