High speed board to board connection

[Saltwater]

Hello,

I want to have a board to board connection that tops out at about 38MHz.
I want to make it as low jitter as possible. But not being formally educated in electronics I wanted to run this by the forum to see if I didnt do something horribly wrong. (Which is very possible)..

Also..Is there a way to guestimate or calculate the right RC values for the range of max 25MHz to 38MHz and possibly smaller?

And is this or the revised version worth building over an optical connection. (albeit for the master clock)?


So.. Here's what I hacked together..

 

[Dan Mills]

PLDs are not usually what you would call low jitter clock sources.
What is your jitter budget?

Generally solid planes are better then trying to get clever with return paths on the digital stuff, and the only clock that actually matters is the one that drives the modulator or the latch if that DAC is R2R, serial clocks just have to meet setup and hold.

Controlled impedance differential routing, and PECL is usually lower jitter then LVDS.

In extremis, coax with transformer coupling gets excellent jitter performance if you do it right.

Regards, Dan.

 

[ads-ee]

High-speed 38 MHz isn't considered high speed in today's technology.

When you say low jitter what is the requirement, <100 fs?

 

[Saltwater]

PLDs are not usually what you would call low jitter clock sources.
What is your jitter budget?

Generally solid planes are better then trying to get clever with return paths on the digital stuff, and the only clock that actually matters is the one that drives the modulator or the latch if that DAC is R2R, serial clocks just have to meet setup and hold.

When you say low jitter what is the requirement, <100 fs?

I don't want to spend the $100,- extra for the phenomenally low jitter option. The board is not cheap already. But connectors are not cheap either. So looking for the go to solution.

Basically, tight enough to do a decent crystal oscillator justice. Also the ad1955 is a decent chip IRC. I'm entertaining the notion to have a section sporting two clocks and a multiplexer for the whole deal. I was thinking the oscillator would run the best if it's on its own little island. Only the connection would be weak link. I do think optical is cool and affordable too. But the schematic involves using pre-amps, so there is a lot inferring the pure signal. So I went from the point it's convenient to have the DAC on another board.. Maybe not the best sounding solution, and i'm trying to overcome this "adequate for human hearing".

Initially my hope was to get a good clock with logic, so it's worry free. And boils down to what I made of it .The FPGA is clocked from a crystal oscillator, and the controller divides the clock with logic "inevitably". I may get away with running the logic alongside the master clock. And meet the latch like that..

 

[FvM]

A comment regarding the diagram in post #1. Instead of load side parallel termination, high level signals (TTL, CMOS) can better use source side series termination, at least for a point-to-point connection without taps.

For real low jitter links that shouldn't be affected by ground bounce and other common mode interferences, you'll use the LVDS I/O standard if your PLD has built-in differntial receivers. Particularly interesting for clocks.

 

[ads-ee]

Basically, tight enough to do a decent crystal oscillator justice. Also the ad1955 is a decent chip IRC. I'm entertaining the notion to have a section sporting two clocks and a multiplexer for the whole deal. I was thinking the oscillator would run the best if it's on its own little island. Only the connection would be weak link. I do think optical is cool and affordable too. But the schematic involves using pre-amps, so there is a lot inferring the pure signal. So I went from the point it's convenient to have the DAC on another board.. Maybe not the best sounding solution, and i'm trying to overcome this "adequate for human hearing".

Initially my hope was to get a good clock with logic, so it's worry free. And boils down to what I made of it .The FPGA is clocked from a crystal oscillator, and the controller divides the clock with logic "inevitably". I may get away with running the logic alongside the master clock. And meet the latch like that..

It seems you a trying to build some sort of audio device that will convert some digital waveform into analog. If this is the plan then splitting everything up into individual islands and running cables to isolate the DAC probably is just making things expensive with very little value. I can see them causing more problems than fixing any noise leakage from the digital portion of the board to the analog portion of the board.

Check out these TI papers on split ground planes with mixed analog digital designs.
https://www.ti.com/lit/an/slyt499/slyt499.pdf
https://www.ti.com/lit/an/slyt512/slyt512.pdf
Pay attention to Fig 6 in slyt512.

 

[Saltwater]

(TTL, CMOS) can better use source side series termination, at least for a point-to-point connection without taps.

I was reading up on it and it seems like something that can be done on dye at the FPGA side, with the the minimal HI input voltage on the DAC being 2.2V and the LOW voltage 0.8V. But.. If the termination is good for 50% reduction 3.3V is not going to drive logic. AFAIK cyclone 3/5 devices do not drive harder than 3.3V.

Still I like it better if it turns out to work, Based on this image I'm struggling to grasp why the grounds (at connector sides?) do not **** up all the current. I see why simple is better, but how does this pan out against the notion that the return path should be close to the signal path?

It seems you a trying to build some sort of audio device that will convert some digital waveform into analog. If this is the plan then splitting everything up into individual islands and running cables to isolate the DAC probably is just making things expensive with very little value.

It's planned to be 3 boards (logic power and DAC) in the "prototyping" phase at least. Can use my own stuff to drive the logic and power for now. I understand it will most likely be worse. Else it would be harder to grasp for me. So the clock will end up on the logic side of things.

I will take the time to read this properly. It seems to detail how to bridge the A and D grounds better and putting two zeners across. I was going for a system star ground. This looks like a more solid solution, than what I had in mind. But inherntly double once more?

 

[Dan Mills]

It is a bog standard delta sigma part, and looks like MClk wants to be 512Fs, so fairly standard (22.5792Mhz and 24.576Mhz are off the shelf for exactly this use).

The usual approach is to derive MClk directly from a suitable osc, which also feeds the divider chain to produce the bit clock and LR clock, MClk drives the modulator and is the only one that is meaningfully jitter sensitive, hence it is driven directly by the osc and not via any sort of PLD.
I would be putting the oscillator on the DAC board and bringing a buffered copy of mclk off to drive the logic, but that is just me.

A 4 Layer board, with solid buried ground plane is almost always a much better starting point then messing around with star earthing (Which you only see in amateur hour audio designs, the pros do planes most of the time), placement is important.

73 Dan.

- - - Updated - - -

Do NOT do the two diode thing.

There is a dirty little detail hidden in some of the better DAC datasheets, the DAC AGND and DGND pins are separate because otherwise ON CHIP parasitic inductance due to the bond wires causes problems.
They are often best tied to a common plane (And even when separate planes are used there are usually tight requirements on maximum voltage differential between them, and is usually less then a diode drop).

Regards, Dan.

 

[FvM]

I would opt for Dan Mills' single plane suggestion.

There's a funny thing with Fig 6 in the TI application note slyt512. They really say:

System star ground DGND connections should be right below each mixed signal device

How do you imagine a system star ground with multiple mixed signal devices and a star point below each device? Sounds like a contradiction in terms.

 

[Saltwater]

A 4 Layer board, with solid buried ground plane is almost always a much better starting point then messing around with star earthing (Which you only see in amateur hour audio designs, the pros do planes most of the time), placement is important.

Ah it's not very apparent. but the star grounding is between three boards to a common ground before the psu side. Which are all "if not two" boards with a big fat ground plane. The line after the DAC suggests the only break I want to make in the groundplane "for this sketch". diverting some analog 12V stuff away from the IC.

The ground via's were ment to be on the top layer, as well as the SMD connector and the arriving lines . Only to dump inside the first via they meet into the digital groundplane at the logic board. Seeing I still believe it is going to get enough current across the cable to drive the logic on the other side. Still wondering if I may be horribly wrong.

But I digg the clock on the DAC. For shure that will be tightest sounding.

 

[D.A.(Tony)Stewart]

I see a lot of design issues with this interface including the RC filters which have no purpose as shown.

Beware that as logic currents change, there will be noise that couples into the DAC analog reference for ground voltage from logic loop currents, rise time for ESR & ESL. This results in dynamic DAC error voltages.

Logic input capacitance and switching peak current has not been addressed. This can cause monotonic errors without details for impedance and timing. This is a common problem with Video DAC's.

Without more details on the design specs, components and signals, I would hold back advice.

 

[Saltwater]

Im very tired right now, long day.. But, it's ment to be rolled of to a point I hit a harmonic that suits my needs. All lines with the same walue, so there are no phase issues between channels.

About the schematic, would running the grounds back through the wire to the logic plane cause any issues?

 

[Saltwater]

Alright.. Here's a version that reflects better what my goal was..Contrary to what I can do in these programs it's still very ugly. And besides the point I'm going to move the clock to the DAC board. :thumbsup:
My worries are, would this reflect the AC termination implemented?

Also I figured that my RC constant should be higher than the propagation delay.
Which for my 10cm flatcable + ~5cm trace is estimated to be 0.75ns.
Giving me values of ~1k and 0.8pF. (.9pf for ±.1pF if i'm cheap)

 

[FvM]

Ribbon cable transmission line impedance (single ended) can be expected in a 60 to 100 ohms range, PLD source impedance probably 20 to 50 ohms depending on the drive strength. 1k/1pF termination is almost open circuit compared to cable impedance and can be safely omitted without changing waveforms much. Why don't you refer to termination schemes suggested in digital logic circuit literature?

Regarding grounding, it's essentail that the return for high speed logic signals is in the cable. The additional ground wire is meaningless for high speed signalling due to it's loop inductance. A problem could arise if ground currents are injected between both grounds, either large DC and low frequency currents that cause relevant voltage drops. Or fast pulsed currents that can affect logic signals also at lower magnitude.

 

[Saltwater]

Why don't you refer to termination schemes suggested in digital logic circuit literature?

Offcourse, the transmission line delay I got from some flatcable datasheet, and added some delay.
The most meaningfull reference I found thus far was this one,
https://www.ti.com/lit/an/scaa045a/scaa045a.pdf

Regarding grounding, it's essentail that the return for high speed logic signals is in the cable. The additional ground wire is meaningless for high speed signalling due to it's loop inductance. A problem could arise if ground currents are injected between both grounds, either large DC and low frequency currents that cause relevant voltage drops. Or fast pulsed currents that can affect logicsignals also at lower magnitude.

Ok so if I understand correctly, that is mostly down to the paths the current will take?. Since I have to drop the return path somewhere, running it through a cable to ground is a similar violation.. I find that very hard to understand.

 

[Dan Mills]

Currents always flow in loops, this is basic.
The bigger the loop area the more energy in the magnetic field set up by the circulating current, and the higher the AC loop impedance, so for best high frequency signal integrity you **Really** want there to be a good way for the high speed currents to get back to the logic board via a path that minimizes loop area (Star earthing does NOT do this, which is why nobody sane uses it in mixed signal designs, hierarchical grounds are another story, but complicated to do well).

This is why on interfaces running over ribbon at any sort of speed you usually see every other line being a ground.

If it were me, I would use a single plane maybe necked down under the DAC with all the digital stuff on one side and all the analogue on the other (Clock is analogue!), clock on the DAC board and a buffered clock fed via the ribbon to the logic board. Every other wire in the ribbon would tie the logic and digital side of the DAC ground planes together.

It is critical that NO signals cross a split or slit in a ground plane.

Now, apart from the MCLk line, none of the other clocks are even slightly fast (and none are particularly jitter sensitive), I would use this and source terminate on the logic board to get the edge rates right down (Maybe 100 ohms), and would just forgo the termination on the DAC board entirely!

The 'star point' if you insist on their being one is the ground plane right under the chip, but I would not bother.

Howard Johnson and Henry Ott are both well worth reading for more then you ever wanted to know about this stuff (Also Tony Walderon and Bill Whitlock for a more audio based view).

Regards, Dan.

 

[D.A.(Tony)Stewart]

The essence of this thread is how to transport 38MHz parallel logic signal with signal integrity to avoid logic errors, crosstalk to analog DAC output and minimize EMI radiation.

ALthough not seriously high speed, crosstalk can become significant.

The basic principals for logic signal integrity are controlled impedance from end to end using interleaved grounds for unbalanced drivers.

You have interleaved grounds but no ribbon cable defined with selected impedance.

The most common parallel interface cable was used on all HDD's before SATA was 100 Ohms unbalanced interleaved grounds. It with 28 AWG wire on .050 inch centers permits mass termination to IDC connectors The PVC dielectric and ratio of diameter to gap is what yields the characteristic impedance of 100 Ohms single ended, unbalanced. FYI, If used with balanced differential pairs it is actually 168 Ohms due to a difference in common mode impedance.

Capacitance: 15.0 pF/ft [ 49.2 pF/m ]
Inductance: 0.15 μH/ft [ 0.49 μH/m ]
Propagation Delay: 1.51 ns/ft [ 4.95 ns/m ]
Velocity of Propagation: 68%

The most common miniature interface today for parallel signals is an FPC connector and FPC flat cable.

Since CMOS used in PLD's is fairly symmetrical impedance these days with ALV devices, the impedance is either 25 or 50 Ohms depending on the device Vol/Iol data in the spec.

Optimal signal margin is a tradeoff between signal attenuation from loading and noise due to mismatch. So depending on signal levels e.g. 3 or 3.3 or 5V, noise margins must be designed so that ripple decay, over/undershoot is settled and beyond worst case input thresholds.

Depending on rise time, prop delay and mismatch resonant decay times, termination options include;
1) nothing for short paths on same board or shield.
2) active termination to V/2 (e.g. SCSI bus)
3) pullup R of several hundred Ohms. ( asymmetric margins)
4) Pullup/pulldown R to V/2
The optimum value of R depends on the minimum loss of margin due to voltage divider drop =load/(source+load) + ripple value at clock edge. keeping mind any aggregate power dissipation from one IC driver.(PLD)

When I interfaced a Kopin AMLCD chip for a wearable TV.VGA monitor with a CPLD driving the sync signals, from an i-pod size package on the hip, I chose to use 270 Ohm pullup on logic and 75 Ohm analog terminations. (circa 1999)

Pls note series RC terminations are not suited to signals other than 50% duty cycle.

 

[Saltwater]

Ok so if I understand correctly I can pull up the signal, and return through the cable. Without grounding the cable at all. In return tying both boards to a common potential?

Yes I think pulling it up will be good enough. The thing that would be nagging me would be correlated reflections attenuating my signal. Possibly even to the point it would not drive logic.

 

[Saltwater]

@Dan Mills , I was just reading the papers you proposed, "or at least some papers". And besides not wanting to have a split groundplane for the DAC for the reasons of, the pins being the separation, and the reference schematic I have is using a solid groundplane as well. The papers actually suggested for me to do otherwise. i.e. split it up because it's a 24-bit DAC. So.. I'm currently still out on that one.

I have planned in the break, (also visible in the picture) so that 12V from the op-amps does not leak into the DAC. So the DAC is on a solid plane. And it's the cards being star grounded, not the board. "yet?" And even the break makes me wonder if the output signal from the DAC likes to travel over the gap. I assume that would not be the case. May need some more browsing around to find more ways to do this proper routing that gets talked about. Seeing I have all the freedom to route it to my best abilities. (3 days into PCB routing

But enough about the board, the reason I'm reluctant to ground the ribbon cable is that it will draw all the crap over the the transmission line to the digital board or vice versa. Having the cards star grounded gives me the opportunity to move the path of least resistance/impedance around in my favor.

http://www.hottconsultants.com/techtips/split-gnd-plane.html
http://www.sigcon.com/Pubs/edn/adcgrounding.htm

 

[ads-ee]

But enough about the board, the reason I'm reluctant to ground the ribbon cable is that it will draw all the crap over the the transmission line to the digital board or vice versa. Having the cards star grounded gives me the opportunity to move the path of least resistance/impedance around in my favor.

Having a ribbon cable with no ground connections and running that between boards is synonymous with split ground planes, i.e. running signal across a gap in the ground reference.

Not grounding the ribbon cable will result in very large ground loops as the signals crossing over the ribbon cable will have NO return path except through your power supply ground.

I'm not sure you are reading good papers on grounding if they suggest doing what you seem to be proposing.

One ground plane for both digital/analog physically separate the digital logic from the analog, splits are okay but not absolutely necessary but a connection between the analog/digital planes should be under the entire DAC and all digital/analog signals that cross between analog/digital parts of the board should cross over the ground connection. Physically keeping the logic for digital and analog separated with adequate decoupling of the digital side of the board, should be more than enough.

If you plan on keeping you star ground then don't run wires (i.e. ribbon cable over the gaps), instead I suggest you use fiber and laser diodes to have 100% electrical isolation between the boards. Or use optocouplers (slow) and have the ribbon cable ground connected to the ground of the source board and the optocoupler. Of course this is more expensive and probably doesn't do much but make you think you've got a better grounding scheme.

I'd sure like to see some of these "papers" that say you should use star grounds and floating ungrounded "ground" wires in a ribbon cable. Recommendations that state things like only grounding one side of something are usually talking about a shield around a cable. This is to avoid creating ground loops with different pieces of equipment that are plugged into different wall AC sockets.