Dec 22, 2012 #1 G gopi_vlsi Junior Member level 1 Joined Mar 25, 2012 Messages 16 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,372 AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates suggest me or guid me regading this is the circuit correct ? Attachments async reset latch.png 33.8 KB · Views: 106
AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates suggest me or guid me regading this is the circuit correct ?
Dec 24, 2012 #2 G gopi_vlsi Junior Member level 1 Joined Mar 25, 2012 Messages 16 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,372 is that transistor level schematic right . Or i should use any gate level one. suggest me
Jan 3, 2013 #3 G gopi_vlsi Junior Member level 1 Joined Mar 25, 2012 Messages 16 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,372 is that transistor level schematic right . Or i should use any gate level one. suggest me
Jan 6, 2013 #4 L legend03u8z Newbie level 3 Joined Mar 22, 2012 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,305 hi, it is right;-) oh, I should say it works, because there are many ways to locate the reset PMOS.