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Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization

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gopi_vlsi

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AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates
suggest me or guid me regading this is the circuit correct ?
 

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    async reset latch.png
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is that transistor level schematic right . Or i should use any gate level one. suggest me
 

is that transistor level schematic right . Or i should use any gate level one. suggest me
 

hi, it is right;-)

oh, I should say it works, because there are many ways to locate the reset PMOS.
 

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