Helping define DC-Potential of capacitive voltage divider through parasitics

[oscarcot]

Hello,

I'm designing a Fully-Differential low noise amplifier for neural signals like the one on the next links:

**broken link removed**
https://www.uni-ulm.de/en/in/instit...or-multi-channel-neural-signal-recorders.html

The amplifiers generate the gain through the capacitor ratio and use a pseudo-resistor (PR) to act as a high-pass filter. As you can see, the input nodes of the amplifier (+) and (-) are between a capacitive voltage divider, so they are kind of floating. Theoretically, the feedback caps C2 should be discharged by the pseudoresistor, bringing the (+) and (-) nodes to the output DC potential. Nevertheless, the pseudoresistor has a very high resistance, usually in Teraohm range, so maybe spectre considers it directly as non-conducting for the DC-analysis.

My problem is: for my layout, the analog-extracted simulation takes the (+) and (-) potentials to 2V, which is already out of the input range of my amplifier. I would like to be able to take this potential to 1V or 1.5V, so my amplifier can work.

To localize the source of the problem, I did the following:
1. I took away all the elements of the circuit, (LNA, CMFB, current sources) and defined the outputs at 1.5V. At the end, only the capacitive voltage divider was there. Vin= 0V, Vout=1.5 and the result was: V(+) = V(-) = 2 V!!, which makes no sense for me. Anyway, this means that the problem was not being caused by my amplifier layout or even the PR.

2. I put all the blocks back, but took out the input caps C1 (C1,C3 for second link) and simulated them as ideal. The V(+) and V(-) were defined as 1.5, which was in the correct input range. I guess this means, only the parasitics of the input caps are causing the problem.

3. I changed the MIM input caps to Poly on Difussion caps, which require substrate contacts connected to GND. Now the voltage V(+) and V(-) go down to 0.3 V, which is also out of range. This helps me think, that at least something can influence this potential.

I tried to make a voltage divider with diodes, hoping to force the simulator to define the voltage at 1.5V. I also connected small resistors which have substrate contacts, but none of these affect the DC solution. I reduced the gmindc and gmin value to 0.01 pS, which helps, but still doesn't bring the potential to the right range.

Does anybody have an idea?
Thanks in advance.
Oscar

 

[FvM]

It's not clear if you are talking about a simulation or real circuit problem.

In simulation, you can always force a DC bias somehow.

In the real circuit, you have to ask if the bias concept (the so-called "peudo resistors") will be sufficient to achieve a suitable operation point. If this doesn't work you should reconsider the concept. I notice that the first link (besides using a fully differential amplifier) has also switches to reset the bias potential.

What I would do is to enforce an "ideal" (or intended) operation point by .IC statements and check the behaviour. If the operation point still drifts out of range, you have obviously unexpected leakage currents in your circuit that need to be reduced or compensated.

 

[oscarcot]

It's not clear if you are talking about a simulation or real circuit problem.

In simulation, you can always force a DC bias somehow.

In the real circuit, you have to ask if the bias concept (the so-called "peudo resistors") will be sufficient to achieve a suitable operation point. If this doesn't work you should reconsider the concept. I notice that the first link (besides using a fully differential amplifier) has also switches to reset the bias potential.

What I would do is to enforce an "ideal" (or intended) operation point by .IC statements and check the behaviour. If the operation point still drifts out of range, you have obviously unexpected leakage currents in your circuit that need to be reduced or compensated.

Thanks. First of all, I'm talking about a simulation using the analog_extracted file. By the way, the problem does not happen with the pure schematic simulation.

Now, for the pseudo-resistors, I tested them on a real chip. Inside it, there is an RC low-pass filter. The C is connected to ground and the output of the filter is connected to an internal voltage follower. Curiously, the cap potential is in a very similar situation: it's like floating, while the PR slowly charges/discharges it. At the end, the PR effectively takes the cap terminal to the input DC voltage. Since the behavior seems right, I assume the PR should also slowly discharge the feedback cap C2.

About the switches, yes, they're one of my next simulation steps.

When I use .IC-statements to enforce the correct operating point, (which gives a correct AC and noise simulation) the potential drifts back to the incorrect point. Therefore, I think that's for some reason the final DC-point calculated by the simulator. Any idea of how to compensate the leakage currents? I have thought about wells, substrate contacts, and stuff like that, but I'm not so experienced in parasitics. Any idea?

Thanks,
Oscar

 

[BradtheRad]

When capacitors are hooked up in series, and a DC voltage is present, the capacitors' final charge levels can be unpredictable.

There is a chance this is supposed to be remedied by adjusting Vtune (shown in schematic in your first link). The article speaks of "tuning the biasing voltage of the first stage pre-amplifier". Perhaps this is by adjusting Vtune, even though it is also used to adjust the filter frequencies.

Or else by a method not shown but rather which is assumed the reader knows about (example, DC offset which the op amp might have terminals for you to make the adjustment).

Your second link shows a schematic which appears to be simplified. Perhaps something was omitted, in order to emphasize the concept of the circuit. Could the same have been done with the other schematic?...(Even though it appears more complete.)

Authors have a tendency to abbreviate an article, rather than to give readers every secret. It is in their financial interest because they want you to buy their manufactured IC.

 

[oscarcot]

When capacitors are hooked up in series, and a DC voltage is present, the capacitors' final charge levels can be unpredictable.

There is a chance this is supposed to be remedied by adjusting Vtune (shown in schematic in your first link). The article speaks of "tuning the biasing voltage of the first stage pre-amplifier". Perhaps this is by adjusting Vtune, even though it is also used to adjust the filter frequencies.

Or else by a method not shown but rather which is assumed the reader knows about (example, DC offset which the op amp might have terminals for you to make the adjustment).

Your second link shows a schematic which appears to be simplified. Perhaps something was omitted, in order to emphasize the concept of the circuit. Could the same have been done with the other schematic?...(Even though it appears more complete.)

Authors have a tendency to abbreviate an article, rather than to give readers every secret. It is in their financial interest because they want you to buy their manufactured IC.

I think, either there's a magic secret to define that potential, or the problem doesn't happen at all in the real chip. Since my PR does work in silicon as expected, I have started to think this might just be a kind of convergence problem.

I'm gonna check if adding the switch transistor helps defining the potential.

Thanks,
Oscar