Help with Verilog simulation

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varunvats69

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simulation for inout in verilog

Hi,

I designed a 2 to 1 Mux using a bufif1 and a bufif0 (file attached).
The simulation results (wave.jpg) show that the output OUT goes into unknown state x at two instances, one at the beginning and another when S (ctrl input) transitions to 1 from 0. Can anyone explain this behavior? I used typical delay values while simulating. It seems to me it is because of the signal inputs (in0 and in1) and the control input S changing simultaneously, because the second x didn't occur when I changed the signal inputs in0 and in1 8 time units after the ctrl input S. However, I haven't been able to convince myself of this.
**broken link removed**
 

verilog simulation

What do all the values mean in the bufif* parameters? This is more parameters than I am use to.

#(1:2:3, 3:4:5, 5:6:7)

Anyways,at least some of these are the rise, fall, and to-Z delays of the buffers. Since they all differ, there is some overlap and they could both be hi-z or transmitting at the same time.

Try this... give each buf a separate output (out0 and out1) and re-sim. You should then be able to see the overlay b/w 44-46ns.
 

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