varunvats69
Junior Member level 1
simulation for inout in verilog
Hi,
I designed a 2 to 1 Mux using a bufif1 and a bufif0 (file attached).
The simulation results (wave.jpg) show that the output OUT goes into unknown state x at two instances, one at the beginning and another when S (ctrl input) transitions to 1 from 0. Can anyone explain this behavior? I used typical delay values while simulating. It seems to me it is because of the signal inputs (in0 and in1) and the control input S changing simultaneously, because the second x didn't occur when I changed the signal inputs in0 and in1 8 time units after the ctrl input S. However, I haven't been able to convince myself of this.
**broken link removed**
Hi,
I designed a 2 to 1 Mux using a bufif1 and a bufif0 (file attached).
The simulation results (wave.jpg) show that the output OUT goes into unknown state x at two instances, one at the beginning and another when S (ctrl input) transitions to 1 from 0. Can anyone explain this behavior? I used typical delay values while simulating. It seems to me it is because of the signal inputs (in0 and in1) and the control input S changing simultaneously, because the second x didn't occur when I changed the signal inputs in0 and in1 8 time units after the ctrl input S. However, I haven't been able to convince myself of this.
**broken link removed**