Help with Verilog code for switch LCD display fpga

[yamcake01096]

Hi, im new in verilog coding, i need help for the 2-line LCD display in Altera DE2 board
I want to write a coding when switch 1 on, it will change the text in display and address value, and for the switch 2
I have compiled the coding and found some error, so someone help me solve the problem?

always @(posedge CLOCK_50 or negedge SW[1])
begin
lcd_stat<=0;
addr	<=23'h000000;
max_addr<=23'h050000;
end

always @(posedge CLOCK_50  or negedge SW[2])
begin
lcd_stat<=1;
addr	<=23'h100000;
max_addr<=23'h150000;
end

FAILED-cannot resolve multiple constant driver for net addr

or

always @(posedge CLOCK_50)
begin
if(SW[1])
begin
lcd_stat<=0;
addr	<=23'h000000;
max_addr<=23'h050000;
end

else if(SW[2])
begin
lcd_stat<=1;
addr	<=23'h100000;
max_addr<=23'h150000;
end

end

 

[syedshan]

Dear

You cannot use multiple always blocks to assign a value to a single reg. You can only assign values to them in a single always block.

also make sure that addr and max_addr and lcd_stat are all declared as reg.

so your second code might work. You did not mention if it also show some error.