Help with interview question #2

[richardyue]

Hi, members,
The following is the interview question #2.
What are the setup and hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

 

[anilkumarv]

Setup time is critical for finding the max clock frequency
the setup time is the time interval before the active clock edge during which the data should remain unchanged
Hold time: Time interval after the active clock edge during which the data should remain unchanged

 

[uditkumar1983]

setup time is the time interval before the active clock edge during which the data should remain unchanged
Hold time: Time interval after the active clock edge during which the data should remain unchanged

When there is skew in the circuit the it depends on type of skew (+ve or -ve),which one is critical

 

[blacksmith_vlsi]

Generally, setup time constrain the max frequency that system can archieve. Hold time violation can be fix by back-end CAD tool, espically P&R. Setup time is what we care in design and synthesis phase.
You can shorten setup time by pipelining critical path of your designe.

 

[xstal]

Generally, setup time constrain the max frequency that system can archieve. Hold time violation can be fix by back-end CAD tool, espically P&R. Setup time is what we care in design and synthesis phase.
You can shorten setup time by pipelining critical path of your designe.

Hi, I can understand that setup time is critical for defining the max frequency. Please tell me how and when hold time is violated. How does it affect the circuit performance. Also how can we shorten up the set up time by pipelining the critical path?
Thanks

 

[satyakumar]

Hi,
I will try to answer your question, If not corect feel free to coment.
The flip flop is made of feed back loop formed by invertors, In setup window the output of the flop evaluates to the desired value. The flop will stabilizes when it enters into feed back loop, the feed backing invertor need to drive the input invertor. But the output drive strength of feed back invertor is not sufficient, hence the input vlotage must be stable for hold time period until the feed backing is done to sufficient strength. If it voilates then rise time increase which evatually voilates subsequant operations. This hold time voilation can be fixed even after layout by delaying some inputs.

Thanks to all

 

[xstal]

Hi Satya,

Thanks for the explanation. I had the same concept but i was not sure of it. Can you please explain how after layouting the hold time violations can be fixed? How does delaying the signal help?

Thanks)

 

[satyakumar]

Hi,
Thanks for your reply,
setup time is window before the clock, the data should not change in that window. But every signal cannot exactly become stable at the start of window, there is more probabilty that it stables by some margin before the setup window. Hence if we utilize that margin by pushing the signal with out voilating setup time then hold time can be fixed. pushing is done by adding delay.

 

[bhanuriramesh]

setup time isuseful in calculating the critical fresuency