hello
Yes, I got my code working. well i got it synthised on xilinx ise
I need to create a test bench for it now and having problems.
an someone help me with the test bench for this please? I ran it on multi sim and got an error to do with the c bit being the incorrect size and a few other things mentioning incorrect sizes also.
I have two 'c' variables in my code, one is c_nx= the output of the alu, which is sent to the ff to be timed, the output of this is the actual port output 'c'
so c_nx is not declared as an output.
anyone?
module ALU(a,b,op,clk,resetb,c);
parameter s = 'd1;
output signed[s+15:0]c;
reg signed[s+15:0]c;
input [15:0]a,b;
input [2:0]op;
input resetb;
input clk;
reg signed [s+15:0]c_nx;
//output signed [s+15:0]c_nx;
// port declarations
parameter WIDTH = 'd16;
parameter ADD_AB = 3'b000; // addition -> c = a + b
parameter SUB_AB = 3'b001; // subtraction -> c = a - b
parameter MUL_AB = 3'b010; // multiplication -> c = a * b
parameter AND_AB = 3'b011; // and -> c = a & b
parameter OR_AB = 3'b100; // or -> c = a | b
parameter XOR_AB = 3'b101; // xor -> c = a ^ b
parameter SHIFT_LEFT_A = 3'b110; // shift left -> c = a >> 1
parameter SHIFT_RIGHT_B = 3'b111; // shift right -> c = b >> 1
always @(a or b or op)
case (op)
ADD_AB: c_nx = a + b;
SUB_AB: c_nx = a - b;
MUL_AB: c_nx = a * b;
AND_AB: c_nx = a & b;
OR_AB: c_nx = a | b;
XOR_AB: c_nx = a ^ b;
SHIFT_LEFT_A: c_nx = a >> 1;
SHIFT_RIGHT_B: c_nx = b >> 1;
endcase
always @ (posedge clk)
if (~resetb)
c <= 0;
else
c <= c_nx;
endmodule
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
module ALU_tb ( // no ports; this is a testbench
);
parameter PRD = 10; // ns - according to left-hand argument to the timescale directive
parameter SIMLEN = 100; // clks - number of clks for which to run the simulation
parameter s = 'd1;
parameter WIDTH = 'd16;
// inputs to the DUT are reg types
reg clk,resetb;
reg [15:0]tb_a,tb_b,true_output;
reg [2:0]tb_op;
// outputs from the DUT are wire type
wire signed[15:0]tb_c;
integer i,j,outfile,pat_error;
// instantiate the device under test
ALU my_alu_testbench(.c(tb_c),.a(tb_a),.b(tb_b),.op(tb_op),.resetb(resetb),.clk(clk));
always #5 clk = ~clk; // every 5 nano seconds invert, create period 10ns
initial
begin
$monitor (tb_a,tb_b,tb_c);
outfile = $fopen("tb_c.txt");
if(!outfile) begin
$display("can not write file!");
$finish;
end
pat_error= 0;
resetb= 1'b1;clk=1'b1;a=0;b=0;op=0;
#2 resetb = 1'b0;
#2 resetb = 1'b1;
// test for instruction add
op = 3'b000;
for (i=0;i<65536;i=i+1)
begin
for (j=0;j<65536;j=j+1)
begin
a = i[15:0];b=j[15:0];
#10 true_output = a + b;
if(c!==true_output[15:0])
begin
$fdisplay (outfile, "%b + %b should be %b. but your output is %b." , a,b,true_output,c);
pat_error= pat_error+1;
end
end
end
end
endmodule