#### toffee_pie

##### Newbie level 6

can anyone with verilog skills help me implement this ALU, I wish to firstly get the basic operations functioning before i move onto the more difficult tasks.

It wont compile, I am getting an error with the endmodule part? also do I need another reg to store the overflow bit and work out signed and unsigned outputs?

// VERILOG CODE

// 'timescale 10ns

module ALU (a,b,Cin,Op,clk,resetb,C[s+15:0],s,ov)

output signed C[s + 15:0] ; // 2's compliment signed 16 bit output word

output ov; // The result of addition or subtraction is

// supposed to fit

// within the significant bits used to represent the numbers.

// If ‘n’ bits are used to represent signed numbers

// in 2’s complement

// scheme, then the result must be in the range

// –2n-1 to 2n-1-1.

// If the result does not fit in this range, then an arithmetic

// overflow has occurred, this used for signed operations.

input clk,resetb; // system clock @ 100Mhz , synchronous

// system reset active low

input [2:0] Op; // assigns ALU one of its 8 operand Instruction

input [15:0] a,b; // unsigned 16 bit input operands to ALU

input Cin,s ; // Carry in, Sum In

// internal nodes

wire [15:0] a,b;

reg signed [15:0] c; // output reg

reg signed s;

reg signed ov;

parameter WIDTH = 'd16;

parameter ADD_AB = 3'b000; // addition -> c = a + b

parameter SUB_AB = 3'b001; // subtraction -> c = a - b

parameter MUL_AB = 3'b010; // multiplication -> c = a * b

parameter AND_AB = 3'b011; // and -> c = a & b

parameter OR_AB = 3'b100; // or -> c = a | b

parameter XOR_AB = 3'b101; // xor -> c = a ^ b

parameter SHIFT_LEFT_A = 3'b110; // shift left -> c = a >> 1

parameter SHIFT_RIGHT_A = 3'b111; // shift right -> c = b >> 1

always @ (a or b or op) begin

// Lets do Arithmetic operations

begin

if (op[2:1] == 2'b00) begin

case (op[2:0])

3'b000:c = a + b ; // addition

3'b001:c = a - b ; // subtraction

//3'b010:c = a * b ; //

default:c = 16'bx;

endcase

//overflow = c[15]^c[14];

end

// Lets do Logical operations

else if (op[2:1] == 2'b01) begin

case (op[2:0])

3'b011:c = a & b ; // logical and

3'b100:c = a | b ; // logical or

3'b111:c = a ^ b; // logical exor

default:c = 16'bx;

endcase

endmodule