ddrr
Junior Member level 2
Hi, all
Under the cadence schematic design environment, I get a device symbol from the PDK, then attach it to it's model file. In that case, the simulation result is strange and wrong.
If I get the symbol from the analoglib, the simulation result will be all right.
I don't know what happened here. Is it something wrong with the configuration?
Expecting for your reply! Thanks a lot!
Under the cadence schematic design environment, I get a device symbol from the PDK, then attach it to it's model file. In that case, the simulation result is strange and wrong.
If I get the symbol from the analoglib, the simulation result will be all right.
I don't know what happened here. Is it something wrong with the configuration?
Expecting for your reply! Thanks a lot!