Prabha Murugesan
Newbie level 3
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity memblk is port ( d : in STD_LOGIC_VECTOR (7 downto 0); we : in STD_LOGIC; addr : integer; o : out STD_LOGIC_VECTOR (7 downto 0)); end memblk; architecture Behavioral of memblk is type lxn is array (0 to 255) of std_logic_vector(7 downto 0); signal tem: lxn:=("00000001","00000010","00000011","00000100", "00000101","00000110","00000111","00001000", "00001001","00001010","00001011","00001100", "00001101","00001110","00001111","00010000", "00010001","00010010","00010011","00010100", "00010101","00010110","00010111","00011000", "00011001","00011010","00011011","00011100", "00011101","00011110","00011111","00100000", "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ", "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ", "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ", others=>"ZZZZZZZZ"); begin process(d,we,addr) begin if(we='0')then tem(addr)<=d; else o<=tem(addr); end if; end process; end Behavioral;
Error:fatal error in process line