help to clear fatal error

[Prabha Murugesan]

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity memblk is
    port ( d : in  STD_LOGIC_VECTOR (7 downto 0);
           we : in  STD_LOGIC;
           addr : integer;
           o : out  STD_LOGIC_VECTOR (7 downto 0));
end memblk;
 
architecture Behavioral of memblk is
 
 
type lxn is array (0 to 255) of std_logic_vector(7 downto 0);  
signal tem: lxn:=("00000001","00000010","00000011","00000100",
                         "00000101","00000110","00000111","00001000",
                         "00001001","00001010","00001011","00001100",
                          "00001101","00001110","00001111","00010000",
                          "00010001","00010010","00010011","00010100",
                          "00010101","00010110","00010111","00011000",
                          "00011001","00011010","00011011","00011100",
                          "00011101","00011110","00011111","00100000",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                           others=>"ZZZZZZZZ");
begin
process(d,we,addr)
begin
if(we='0')then
tem(addr)<=d;
else
o<=tem(addr);
end if;
end process;
end Behavioral;

---

Error:fatal error in process line<=tem(addr)

 

[aruipksni]

your problem is probebly because you are using address the is out of 0 to 255 range.

instead of integer , use type like : "addr : natural range 0 to 255;"
then in your simulation generate values beetween those bounds.

 

[TrickyDicky]

How about re-using your old thread, instead of re-posting the same thread again?

And you STILL didnt post the error - you just posted the line the error was on!

 

[vlsi_whiz]

RAM should be modeled in the following way. RAM modeled without clocks will mostly infer Latches.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity RAM is

  generic (	K: integer:=8; -- number of bits per word
			W: integer:=8); -- number of address bits

  port (WR: in std_logic; --active high write enable
		ADDR: in std_logic_vector(W-1 downto 0); -- RAM address
		DIN: in std_logic_vector(K-1 downto 0); -- write data	
		DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end entity RAM;

architecture RAMBEHAVIOR of RAM is
  
  subtype WORD is std_logic_vector ( K-1 downto 0); -- define size of WORD
  type MEMORY is array (0 to 2**W-1) of WORD; -- define size of MEMORY
  signal RAM256: MEMORY; -- define RAM256 as signal of type MEMORY

begin
process (WR, DIN, ADDR)
  variable RAM_ADDR_IN: integer range 0 to 2**W-1; -- to translate address to integer
  variable STARTUP: boolean :=true; --temporary variable for initialization
  begin
    if (STARTUP = true) then -- for initialization of RAM during start of simulation
		RAM256 <= ( 0 => "00000101", -- initializes first 5 locations in RAM
					1 => "00110100", -- to specific values
					2 => "00000110", -- all other locations in RAM are
					3 => "00011000", -- initialized to all 0s
					4 => "00000011",
					others => "00000000");
		DOUT <= "XXXXXXXX"; -- force undefined logic values on RAM output
		STARTUP :=false; -- now this portion of process will only execute once
   else
		RAM_ADDR_IN := conv_integer (ADDR); -- converts address to integer
		if (WR='1') then -- write operation to RAM
			RAM256 (RAM_ADDR_IN) <= DIN ;
		end if;
			DOUT <= RAM256 (RAM_ADDR_IN); --always does read operation
		end if;
end process;
end architecture RAMBEHAVIOR;