In order to avoid latch when coding with verilog, we add "else C<=C" as following:
always @(posedge clk)
begin
if(A==1'b0)
C<=B;
else
C<=C;
end
But for combinational logic, the following code gets problems of timing loop. by the way, C has been assigned to registers before. Could you tell me what is the problem and how to solve it? Thanks a lot.
always @(A or B)
As stated earlier, if you assing C <= C in a clocked always process, you will infer a latch. This is because you are connecting the output back to the input. Feedback. To avoid this and also latch inference, assign C a default value in the IF clause.
Code:
always @(posedge clk)
begin
if(A==1'b0)
C=B;
else
C=1'b0;
end
Always ensure that all the conditions in an IF loop or Case statement are covered to avoid inferring latches.
i hope there is no need to assign a else part in the always block which is sensitive to the posedge clk
here is one example
module d_ff(q,d,clk);
input d,clk;
output reg q;
always @(posedge clk)
begin
if(clk)
q<=d;
end
endmodule
this will synthesis to the d flipflop but in this there is no else part.
vlsi_whiz said:
As stated earlier, if you assing C <= C in a clocked always process, you will infer a latch. This is because you are connecting the output back to the input. Feedback. To avoid this and also latch inference, assign C a default value in the IF clause.
Code:
always @(posedge clk)
begin
if(A==1'b0)
C=B;
else
C=1'b0;
end
Always ensure that all the conditions in an IF loop or Case statement are covered to avoid inferring latches.
in the sequential logic , without else, it is not synthesized latch. But in the combinational logic .it will.
in your combinational code , it is uncorrect. because it will cause combinational loop. i think you can use "assgin" statement replace the always block.