Help: timing loop and latch

[newcpu]

In order to avoid latch when coding with verilog, we add "else C<=C" as following:
always @(posedge clk)

begin

if(A==1'b0)

C<=B;

else

C<=C;

end

But for combinational logic, the following code gets problems of timing loop. by the way, C has been assigned to registers before. Could you tell me what is the problem and how to solve it? Thanks a lot.
always @(A or B)

begin

if(A==1'b0)

C<=B;

else

C<=C;

end

 

[incisive]

Do use blocking assignments in the combo part.

 

[nand_gates]

always @(posedge clk) 
   if(A==1'b0)   C<=B;

Here no need to add else part!

But

always @(A or B) 
begin 
   if(A==1'b0) 
       C<=B; 
   else 
       C<=C; 
end

This will create a latch (combo loop) because here output is fedback to input
if A != 0.

To avoid this use the following code

always @(posedge clk) C_reg <= C;
always @(A or B) 
begin 
   if(A==1'b0) 
       C=B; 
   else 
       C=C_reg; 
end

 

[vlsi_whiz]

As stated earlier, if you assing C <= C in a clocked always process, you will infer a latch. This is because you are connecting the output back to the input. Feedback. To avoid this and also latch inference, assign C a default value in the IF clause.

always @(posedge clk)  
begin 
   if(A==1'b0) 
       C=B; 
   else 
       C=1'b0; 
end

Always ensure that all the conditions in an IF loop or Case statement are covered to avoid inferring latches.

 

[satya_422]

i hope there is no need to assign a else part in the always block which is sensitive to the posedge clk
here is one example

module d_ff(q,d,clk);
input d,clk;
output reg q;
always @(posedge clk)
begin
if(clk)
q<=d;
end
endmodule

this will synthesis to the d flipflop but in this there is no else part.

As stated earlier, if you assing C <= C in a clocked always process, you will infer a latch. This is because you are connecting the output back to the input. Feedback. To avoid this and also latch inference, assign C a default value in the IF clause.

always @(posedge clk)  
begin 
   if(A==1'b0) 
       C=B; 
   else 
       C=1'b0; 
end

Always ensure that all the conditions in an IF loop or Case statement are covered to avoid inferring latches.

 

[megastar007]

Only for combo process,we require else to avoid latches. For register process,no need for else part

 

[michael_chen]

in the sequential logic , without else, it is not synthesized latch. But in the combinational logic .it will.
in your combinational code , it is uncorrect. because it will cause combinational loop. i think you can use "assgin" statement replace the always block.