Hey Guys ! i'm writing a VHDL Code to describe a serial in parallel out shift register -which is not that hard- but the problem is the constraints that's imposed on me by the required project:
its required that if the first bit of the sequence is 1 then the register will begin to recieve data serially, but the problem is i cant do it in VHDL unless i want the register to actually RESET everytime the first bit is a 0,which is wrong... anyways here's my code.....appreciating any help and sorry for the LONG post :/
entity REG isPort( din :inSTD_LOGIC;
clk :inSTD_LOGIC;
data :outSTD_LOGIC_VECTOR(6downto0);
data_valid :outSTD_LOGIC;
err :outSTD_LOGIC);end REG;architecture Behavioral of REG isbeginprocess(clk)variable tmp:std_logic_vector(9downto0);-- it's a variable because i need it to change value variable parity:std_logic;-- instantaneously for other project requirements :/beginif(tmp(9)='0')then tmp :=(others=>'0');elsif(clk'eventand clk='1')then--if first bit of the sequence=1,at the +ve edge..
tmp := din & tmp(9downto1);-- the register begin to recieve input seriallyendif;
First of all , thanks again for the super-fast response
well, the following code tells u what i mean by ''other project requirements''
EDIT: its a shift RIGHT register
process(clk)variable tmp:std_logic_vector(9downto0);variable parity:std_logic;beginif(clk'eventand clk='1')then-- ignoring the start bit condition
tmp := din & tmp(9downto1);endif;--parity is xoring the data(6:0) bits...
parity :=(tmp(8)xor tmp(7)xor tmp(6)xor tmp(5)xor tmp(4)xor tmp(3)xor tmp(2));-- the parallel output is data(6:0).-- tmp(1) is a parity bit => when no of ones in data(6:0) is EVEN...-- parity must equal '0' .-- tmp(0) is a stop bit( =1 when correct transmission is recieved).-- The output signals(err,data_valid) depend on tmp(0,1),-- since the [B]process[/B] is executed [B]concurrent[/B] with [B]other lines of code[/B] -- i have to assign outputs inside process.if(((tmp(1)= '1')and(parity ='0'))or((tmp(1)= '0')and(parity ='1')))then-- i.e if parity checkedif(tmp(0)='1')then-- and stop bit ='1'if(clk'eventand clk='1')then
data <= tmp(8downto2);-- the data output is stored in a new register.endif;endif;endif;
err <=(not tmp(0))or( tmp(1)xor(parity));-- if the stop bit not equal 1
data_valid <=(tmp(0));-- or parity doesn't check then err=1 endprocess;