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HELP: Serial in Parallel Out Shift Register

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metalnumb

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Hey Guys ! i'm writing a VHDL Code to describe a serial in parallel out shift register -which is not that hard- but the problem is the constraints that's imposed on me by the required project:

its required that if the first bit of the sequence is 1 then the register will begin to recieve data serially, but the problem is i cant do it in VHDL unless i want the register to actually RESET everytime the first bit is a 0,which is wrong... anyways here's my code.....appreciating any help and sorry for the LONG post :/


Code VHDL - [expand]
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entity REG is
    Port ( din : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           data : out  STD_LOGIC_VECTOR (6 downto 0);
           data_valid : out  STD_LOGIC;
           err : out  STD_LOGIC);
end REG;
 
architecture Behavioral of REG is
                   
begin
 
process(clk)
 
variable tmp:std_logic_vector(9 downto 0);  -- it's a variable because i need it to change value 
variable parity:std_logic;                             -- instantaneously for other project requirements :/
 
begin
 
if (tmp(9)='0') then tmp :=(others=>'0');  
elsif(clk'event and clk='1')then                    --if first bit of the sequence=1,at the +ve edge..
  tmp := din & tmp(9 downto 1) ;                -- the register begin to recieve input serially
end if;

 

TrickyDicky

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surely it means you just wait until din is '1'. Then use a counter to count values into the shift register.
 

metalnumb

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thanks for your reply , but i dont get it o_O what would i need a counter for ?
 

TrickyDicky

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I dont understand your comment about needing variables. it doesnt behave the way you think it behaves.

in the following code, the process will wait until din = '1'. Then it shifts in the next 7 bits and outputs them all onto data.


Code VHDL - [expand]
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signal count : integer range 0 to 8;
signal tmp   : std_logic_vector(6 downto 0);
 
...
 
shift_proc : process(clk)
begin
  if rising_edge(clk) then
    
    if din = '1' and count = 0 then
      count <= 8;
    end if;
      
    tmp <= tmp(5 downto 0) & din;  
    
    if count > 0 then
      count <= count - 1;
    end if;
      
    if count = 1 then
      data       <= tmp; 
      data_valid <= '1';
    else
      data_valid <= '0';
    end if;
    
  end if;
end process;



edit - changed the din requirements.
 

metalnumb

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First of all , thanks again for the super-fast response ;)
well, the following code tells u what i mean by ''other project requirements''
EDIT: its a shift RIGHT register ;)

Code VHDL - [expand]
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process(clk)
 
variable tmp:std_logic_vector(9 downto 0);
variable parity:std_logic;
 
begin
 
if(clk'event and clk='1')then                        -- ignoring the start bit condition
tmp := din & tmp(9 downto 1) ; 
end if;
 
--parity is xoring the data(6:0) bits...
 
parity := (tmp(8) xor tmp(7) xor tmp(6) xor tmp(5) xor tmp(4) xor tmp(3) xor tmp(2));
 
-- the parallel output is data(6:0).
-- tmp(1) is a parity bit => when no of ones in data(6:0) is EVEN...
-- parity must equal '0' .
-- tmp(0) is a stop bit( =1 when correct transmission is recieved).
-- The output signals(err,data_valid) depend on tmp(0,1),
-- since the [B]process[/B] is executed [B]concurrent[/B] with [B]other lines of code[/B] 
-- i have to assign outputs inside process.
 
                                    
if ( ( (tmp(1) = '1') and (parity ='0') ) 
         or ( (tmp(1) = '0') and (parity ='1') )   ) then
                                                                                  -- i.e if parity checked
if (tmp(0)='1') then                                                     -- and stop bit ='1'
         if (clk'event and clk='1')  then 
 
data <= tmp(8 downto 2) ;                       -- the data output is stored in a new register.
 
end if;
end if;
end if;
 
                                                
err <= ( not tmp(0) ) or ( tmp(1) xor (parity) ); -- if the stop bit not equal 1 
data_valid <= (tmp(0)) ;                       -- or parity doesn't check then err=1 
 
end process;

 

TrickyDicky

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But you still have to clock 8 bits in until you can check the parity. You wont be checking partiy on every clock cycle.

Plus, inside a clocked process, you should only assign anything inside the clocked bit, not outside.
 
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