help reqiured for modeling a delay locked loop in simulink

[vijay_nag]

hi all!

i have been trying to model a dll in simulink but to no results.
i am using the variable transport delay to model the voltage controlled delay line.
can anybody suggest me how many delays i have to include. any links or articles regarding the topic are appreciated.

regards,
vijay

 

[brmadhukar]

Re: help reqiured for modeling a delay locked loop in simuli

Hi,
I guess you are doing it for DSSS. In such a case you need to increase the sample rate to more than 2 samples per bit, else you cannot model the delay effectively.

brmadhukar