module datainout(DataToFPGA, DataFromFPGA, ClrFPGAMem, DataValidToFPGA, DataValidFromFPGA, ClkToFPGA);
input [7:0] DataToFPGA;
output [7:0] DataFromFPGA;
input ClrFPGAMem;
input DataValidToFPGA;
output DataValidFromFPGA;
input ClkToFPGA;
reg [31:0] temp;
reg [7:0] DataFromFPGA;
reg DataValidFromFPGA;
reg [2:0] state;
parameter Sinit = 3'b000;
parameter Sread = 3'b001;
parameter Swrite = 3'b010;
parameter Spause = 3'b100;
integer i;
integer j;
always@ (negedge ClkToFPGA or posedge DataValidToFPGA)
begin
if (ClrFPGAMem)
begin
state = Sinit;
DataValidFromFPGA = 1'b0;
DataFromFPGA = 8'bzzzzzzzz;
end
else
begin
case(state)
Sinit: begin
if(DataValidToFPGA)
begin
i = 1;
state = Sread;
end
else
state = Sinit;
end
Sread: begin
temp[8*(i-1)] = DataToFPGA[0];
temp[8*(i-1)] = DataToFPGA[1];
temp[8*(i-1)] = DataToFPGA[2];
temp[8*(i-1)] = DataToFPGA[3];
temp[8*(i-1)] = DataToFPGA[4];
temp[8*(i-1)] = DataToFPGA[5];
temp[8*(i-1)] = DataToFPGA[6];
temp[8*(i-1)] = DataToFPGA[7];
i=i+1;
if(!DataValidToFPGA)
state = Spause;
end
Spause: begin
i=1;
DataValidFromFPGA = 1'b1;
state = Swrite;
end
Swrite: begin
if(DataValidFromFPGA)
begin
DataFromFPGA[0] = temp[8*(i-1)];
DataFromFPGA[1] = temp[8*(i-1)];
DataFromFPGA[2] = temp[8*(i-1)];
DataFromFPGA[3] = temp[8*(i-1)];
DataFromFPGA[4] = temp[8*(i-1)];
DataFromFPGA[5] = temp[8*(i-1)];
DataFromFPGA[6] = temp[8*(i-1)];
DataFromFPGA[7] = temp[8*(i-1)];
i=i+1;
end
if(i==6) DataValidFromFPGA = 1'b0;
end
endcase
end
end
endmodule