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help! project due tomorrow!

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amr090

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error:xst:899

Trying to get this code to work...it runs fine on simvision..but when i transfer the code onto xilinx...i get problems....

Code:
module datainout(DataToFPGA, DataFromFPGA, ClrFPGAMem, DataValidToFPGA, DataValidFromFPGA, ClkToFPGA);
   input [7:0] DataToFPGA;
   output [7:0] DataFromFPGA;
   input ClrFPGAMem;
   input DataValidToFPGA;
   output DataValidFromFPGA;
   input ClkToFPGA;

   reg [31:0] temp;

   reg [7:0] DataFromFPGA;
   reg DataValidFromFPGA;
   reg [2:0] state;

   parameter Sinit   = 3'b000;
   parameter Sread   = 3'b001;
   parameter Swrite  = 3'b010;
   parameter Spause  = 3'b100;
   
   integer i;
   integer j;

   always@ (negedge ClkToFPGA or posedge DataValidToFPGA)
   begin 
	if (ClrFPGAMem)
	    begin
		state = Sinit;
		DataValidFromFPGA = 1'b0;
		DataFromFPGA = 8'bzzzzzzzz;
	    end
	else
	    begin
		case(state)
		  Sinit: begin
			   if(DataValidToFPGA)
			     begin
			     i = 1;
			     state = Sread;
			     end
			   else
			     state = Sinit;	  
   			 end
		  Sread: begin
		  	       	
   			    
                                temp[8*(i-1)] = DataToFPGA[0];
						  temp[8*(i-1)] = DataToFPGA[1];
						  temp[8*(i-1)] = DataToFPGA[2];
						  temp[8*(i-1)] = DataToFPGA[3];
						  temp[8*(i-1)] = DataToFPGA[4];
						  temp[8*(i-1)] = DataToFPGA[5];
						  temp[8*(i-1)] = DataToFPGA[6];
						  temp[8*(i-1)] = DataToFPGA[7];
			    
			  i=i+1;
			 if(!DataValidToFPGA)
			   state = Spause;
			 end
		  Spause: begin
 			   i=1;
			   DataValidFromFPGA = 1'b1;
			   state = Swrite;
   			 end
		  Swrite: begin
		  	   if(DataValidFromFPGA)
			   begin
			   
   			     
                                DataFromFPGA[0] = temp[8*(i-1)];
						  DataFromFPGA[1] = temp[8*(i-1)];
						  DataFromFPGA[2] = temp[8*(i-1)];
						  DataFromFPGA[3] = temp[8*(i-1)];
						  DataFromFPGA[4] = temp[8*(i-1)];
						  DataFromFPGA[5] = temp[8*(i-1)];
						  DataFromFPGA[6] = temp[8*(i-1)];
						  DataFromFPGA[7] = temp[8*(i-1)];	
			     
			   i=i+1;
			   end
			  if(i==6)  DataValidFromFPGA = 1'b0;
   			 end

	       endcase
	   end
   end
endmodule



Here are the errors!
Code:
RROR:Xst:899 - datainout.v line 27: The logic for <state> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 28: The logic for <DataValidFromFPGA> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[7]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[6]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[5]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[4]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[3]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[2]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[1]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 29: The logic for <DataFromFPGA[0]> does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 33: The logic for [i] does not match a known FF or Latch template.
ERROR:Xst:899 - datainout.v line 33: The logic for <temp[0]> does not match a known FF or Latch template.


There are more errors...but they are all this exact format....if someone could help me out by fixing this code itd be great.

link to the project...
 

maksya

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xst:899

IMHO, you have errors because of this string - always@ (negedge ClkToFPGA or posedge DataValidToFPGA). There is no flip-flop or latch in the digital world that can operate with two clocks. It is impossible to implement this code in FPGA.

In proof of my words try to replace this string with - always@ (negedge ClkToFPGA) and you will see that errors disappeared.

And what about simulation - a lot of language constractions pass the simulation fine, but they are not synthesisable.
 

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