Tcq+Tcombi<=Tclock period-Tsetup-tskew
2ns+3ns<=Tclock period-1ns-1ns
2ns+3ns+1ns+1ns<=Tclock period
7ns<=Tclock period
Frequancy=1/Tclock Period
F=1/7*10-9
Only one thing i cant get is you have given T + tskew - tsetup but the equations in all the above posts points to T - tskew - tsetup. Can you pl explain why this contradiction occurs??
There are terms called, Negative Skew & Positive Skew, defined w.r.t the direction of the clock & input data coming to the design.
w.r.t above terms explanation for the above problem is given in the attached pdf file. Pl go through it.
Based on my interview(s), I prepared this document.
pl find the attachment.
Hope it will help you all. At least it will show the path for STA learnings.
Negative skew play important role in this question.
Postive skew will beneficial for setup , where as negative skew beneficial for hold.
Negative skew means, the capture register is receiving the clock early compared to launch flop. Means, the insertion delay for the launch flop is more than capture flop. With negative skew, the effective clock period will reduce.