Jul 9, 2010 #1 A ali_bukhari Newbie level 6 Joined Mar 24, 2010 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location lhr Activity points 1,349 i ve written a verilog coge for decoding manchester bits which are incapsulated in between sync bits and a parity bit ,i ve written this code using fsm can some 1 remove the logical error or temme why states r nt working?
i ve written a verilog coge for decoding manchester bits which are incapsulated in between sync bits and a parity bit ,i ve written this code using fsm can some 1 remove the logical error or temme why states r nt working?