Help me understand metastability hardened flip-flops

[nitu]

MetaStability Aviodance

Can anybody help me in understanding of metastability hardened flip-flops(FF)? What can be the problem if the FF gets into metastability state ?

Thanks

 

[rfmw]

Re: MetaStability Aviodance

The problem is that flip flop's metastable output affects the circuit behind it, because the flip flop's output doesn't have a defined logic state. Metastability can occur when you have two un-synchronized signals in your circuit. Therefore you must sooner or later synchronize your signals (using flip flops). You can lower the probability of flip flop going into metastable state with series (or chain) of several flip flops or even metastable free flip flops.

Perhaps this link helps with metastability basics: https://www.onsemi.com/pub/Collateral/AN1504-D.PDF

 

[xv_ning999]

Re: MetaStability Aviodance

For some control signals, add two serial register to synchronize them to new clock domain is enough,and for data bus , asynchronous fifo can be used.

 

[nemolee]

Re: MetaStability Aviodance

These will be metastability occured when a signal pass through another different clock domain. You have to use synchronizer to avoid metastable signal producing error logic to next dff.

 

[carrie]

Re: MetaStability Aviodance

attached is a good paper

 

[smith_kang]

Re: MetaStability Aviodance

hi
metastability occures when your flip flop violate the setup and hold time.any violation regarding setup hold time make the output of the FF unstable or force it in to metastable state.however this state is for small duration but it degrade the performance of the circuit.

 

[spauls]

Re: MetaStability Aviodance

Read Digital design by Wakerley,
very good explanation is there

 

[beowulf]

Re: MetaStability Aviodance

Here is the Wakerly book

 

[shakalaka]

Re: MetaStability Aviodance

hey...
Nobody digital circuit can avoid...Mestability.......
rather one can reduce the effect of the same....and can have the idea...when it is going to happen....

when we say Mestability....it means...nither...Zero...nor One.....it is the state between zero and one.... it happens...to every digital circuit..because....every digital circuit/logic.....has interface to external world..(i.e. dependancy of input)...and always....it is Asynchronous........so...to minimize the effect of Metastable state....one can put the several Flops....depending on the calculation of"Mean time Between Failure (i.e. MTBF)......"

hope..this resolves your query....
if not please let me know...
thx