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Help me solve current leakage in a design

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Member level 1
Apr 10, 2002
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characterizing memory current leakage with hsim

I have a design which I found uses excessive current while in
suspend mode when clock is turned off. Is there any good tool
that can help me catch the problem? RTL level or transistor
level will be just fine. Of course I didn't want to run HSPICE.


hsim current leakage 확인

well in general hsim or nanosim should give you chance to fix the problem for larger gate counts quiet efficient.

Powermill is the tool for checking current leakage of whole chip.

nanosim is the successor of powermill ...

I am not able to suggest which tool is better for you, but trying to solve the problem you met. It sound like your design already been the silicon; if yes, you had better to take a photo on the die to check the "hot spot". These "red dots" usually are the source of massive power consumption. In general, the "res dots" are caused by the dangling nets, such as the memory output bus w/o bus-hold circuits. You can also check the input condition is whether floating or ont of bi-directional pads, if it's the reason cause your design so "warm", make use some pull-up/down resistors.

Thanks for the suggestions

Thanks you all for the suggestions.

Did check any short ?
Run hsim and place test for high current like DCpath vdd ?
If you have silicon 'hot spot' is fast and accurate ?
Liquid cistal is less expensive but les accurate and more difficult to setup.

OkGuy ?

You mean h s i m can calculate the static leakage current flowing thru every transistor from layout ? What if chip is multi million gate ?
How is this h s i m compared with nan0sim ?


Hi, PowerMill from synopsys is good for leakage power analysis. Do you use "lv" technology? if yes, the leakage current will be much large than normal technology.

Hsim is good also for that task, even with millions of tr.
It is normaly used to simulation large memory chips.

I have already used HSIM for a very large circuit simulation to get
the leakage current. It is realy good. You can catch also floating
nodes or pass logic problems. Forget gate level ...

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