help me place power IOs in Silicon Ensemble

[triquent]

power ios

My course project spec isthe tool we are using is the silicon ensemble)
1) 2 pairs of VDD VSS pads on four side, spread out on each side
2) Additional power/ground pads sandwich clock pad in IO(only one clock pin in this design)
3) Power connection is completed including IO rings

how to arrange the power pads is better for higher speed?
1) Where should I arrange the VDD&VSS pads on each side? center or corner?
2)for the VDD/VSS pads to sandwich the clock pad, should i use two VDD or two VSS or one VSS&one VDD? which one is better?
3) how to determine where should I place the clock pins and other IO pins? make them as close as to their corresponding internal cell?
4) in order to complete the power connection, I should add the corner cell. how about the filler cell? if yes, at which step to add? also should I use command CONNECT RING? i didn't use it at the class.

 

[mediative]

help place power IOs?

1) first add VDD&VSS pads in top.v, then modify the io file around the core using the order mode
4) add filler cell after route complete.

 

[anjali]

Re: help place power IOs?

placing the VDD pads towards the memories, will reduce the delays. their placement depends on the design.
in general, macros (ex:memories) will be placed at corners to reduce routing congestion.

clock pad placement have to be taken care in clock tree synthesis. and one issue to be remembered here is, near clock pad, placement of reset pad results transitions in reset signal.