MRFGUY
Full Member level 1
I just try to study FSM.
I just wrote a FSM by using verilog. My plan is selling ticket with 15. user are allowed to add 5 or 10. whenever it reach to 15 ticket will come out and back to start state. If it reach to 20, ticket and change 5 and return to start state . It seem ok at this moment. (but let me know what should I change in my program)
But I also want to show in two 7 seg disp. like how much user need to add more to get a ticket. At this point I am not sure how to add.
Should I assume 7 seg into two condition (present led and next led).
I've attached my program here.
Thanks
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:15:08 08/29/05
// Design Name:
// Module Name: sell_ticket
// Project Name:
// Target Device:
// Tool versions:
// Description: Selling ticket with 15. If user add 15 only ticket will come out.
// If user add 20 the machine chnage 5 and ticket will come out.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sell_ticket(a, b, reset, clk, t, c);
input a, b, reset, clk; //a is 5$ input and b is 10 $ input
output t, c; // c is coin change and t is ticket
reg t, c;
reg [2:0] state, next_state;
parameter zero=3'b000;
parameter five=3'b001;
parameter ten=3'b010;
parameter fifteen=3'b011;
parameter twenty=3'b100;
always @(posedge clk)
begin
if (reset)
state<=zero;
else
state <= next_state;
end
always @(a,b,state)
begin
case (state)
zero: case({b,a})
2'b00 : next_state= zero;
2'b01 : next_state= five;
default : next_state = ten;
endcase
five: case({b,a})
2'b00 : next_state= five;
2'b01 : next_state= ten;
default : next_state = fifteen;
endcase
ten: case({b,a})
2'b00 : next_state= ten;
2'b01 : next_state= fifteen;
default : next_state = twenty;
endcase
default :next_state = zero;
endcase //state state case end
end //always end
always@(state)
begin
case(state)
fifteen : {t,c}= 2'b10;
twenty : {t,c} = 2'b11;
default : {t,c} = 2'b00;
endcase
end
endmodule
I just wrote a FSM by using verilog. My plan is selling ticket with 15. user are allowed to add 5 or 10. whenever it reach to 15 ticket will come out and back to start state. If it reach to 20, ticket and change 5 and return to start state . It seem ok at this moment. (but let me know what should I change in my program)
But I also want to show in two 7 seg disp. like how much user need to add more to get a ticket. At this point I am not sure how to add.
Should I assume 7 seg into two condition (present led and next led).
I've attached my program here.
Thanks
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:15:08 08/29/05
// Design Name:
// Module Name: sell_ticket
// Project Name:
// Target Device:
// Tool versions:
// Description: Selling ticket with 15. If user add 15 only ticket will come out.
// If user add 20 the machine chnage 5 and ticket will come out.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sell_ticket(a, b, reset, clk, t, c);
input a, b, reset, clk; //a is 5$ input and b is 10 $ input
output t, c; // c is coin change and t is ticket
reg t, c;
reg [2:0] state, next_state;
parameter zero=3'b000;
parameter five=3'b001;
parameter ten=3'b010;
parameter fifteen=3'b011;
parameter twenty=3'b100;
always @(posedge clk)
begin
if (reset)
state<=zero;
else
state <= next_state;
end
always @(a,b,state)
begin
case (state)
zero: case({b,a})
2'b00 : next_state= zero;
2'b01 : next_state= five;
default : next_state = ten;
endcase
five: case({b,a})
2'b00 : next_state= five;
2'b01 : next_state= ten;
default : next_state = fifteen;
endcase
ten: case({b,a})
2'b00 : next_state= ten;
2'b01 : next_state= fifteen;
default : next_state = twenty;
endcase
default :next_state = zero;
endcase //state state case end
end //always end
always@(state)
begin
case(state)
fifteen : {t,c}= 2'b10;
twenty : {t,c} = 2'b11;
default : {t,c} = 2'b00;
endcase
end
endmodule