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help me in interconnecting two verilog modules

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laginhanu

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Hi friends will you please help me
module top (Tte, Clk, resetn, out);
input Tte;
input Clk;
input resetn;
output [35:0] out;
…………….
…………….
endmodule
The above module generates the output for 36 bit LFSR. Now I have to give this output of lfsr as input to the c432 bench mark circuit which has a top level module like this
module TopLevel432b (E, A, B, C, PA, PB, PC, Chan);
input[8:0] E, A, B, C;
output PA, PB, PC;
output[3:0] Chan;
wire[8:0] X1, X2, I;
PriorityA M1(E, A, PA, X1);
PriorityB M2(E, X1, B, PB, X2);
PriorityC M3(E, X1, X2, C, PC);
EncodeChan M4(E, A, B, C, PA, PB, PC, I);
DecodeChan M5(I, Chan);
endmodule /* TopLevel432b */

HI FRIENDS NOW WILL YOU PLEASE HELP ME ABOUT HOW TO COMBINE THESE TWO MODULES
 

sachingorkhe

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Lower LSBs of 1st module can be connect to LSBs of the 2nd module.
You can connect at top level module as per the following -

out(36:28) => E(8:0);
out(27:19) => C(8:0);
out(18:10) => B(8:0);
out(9:0) => A(8:0);

Hope this helps.

~Sachin
 

ramesh.balaram

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if you have doubt regarding only inter-connection of module then
this is how i can apply ......

module top_high;
reg Tte_reg;
reg clk_reg;
reg resetn_reg;
wire [35:0]out_wire;

reg [8:0]E_reg;
reg [8:0]A_reg;
reg [8:0]B_reg;
reg [8:0]C_reg;

wire PA_wire,PB_wire,PC_wire;
wire [3:0] chan;

always begin
E_reg = [8:0]out_wire;
A_reg = [17:9]out_wire;
B_reg = [26:18]out_wire;
C_reg = [35:27]out_wire;
end

module top (
.Tte(Tte_reg),
.Clk(clk_reg),
.resetn(resetn_reg),
.out(out_wire)
);

module TopLevel432b (
.E(E_reg),
.A(A_reg),
.B(B_reg),
.C(C_reg),
.PA(PA_wire),
.PB(PB_wire),
.PC(PC_wire),
.Chan(chan_wire)
);
endmodule

this is my basic idea..... please check for any errors
 

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