Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help me in interconnecting two verilog modules

Status
Not open for further replies.

laginhanu

Newbie level 1
Joined
Dec 14, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,291
Hi friends will you please help me
module top (Tte, Clk, resetn, out);
input Tte;
input Clk;
input resetn;
output [35:0] out;
…………….
…………….
endmodule
The above module generates the output for 36 bit LFSR. Now I have to give this output of lfsr as input to the c432 bench mark circuit which has a top level module like this
module TopLevel432b (E, A, B, C, PA, PB, PC, Chan);
input[8:0] E, A, B, C;
output PA, PB, PC;
output[3:0] Chan;
wire[8:0] X1, X2, I;
PriorityA M1(E, A, PA, X1);
PriorityB M2(E, X1, B, PB, X2);
PriorityC M3(E, X1, X2, C, PC);
EncodeChan M4(E, A, B, C, PA, PB, PC, I);
DecodeChan M5(I, Chan);
endmodule /* TopLevel432b */

HI FRIENDS NOW WILL YOU PLEASE HELP ME ABOUT HOW TO COMBINE THESE TWO MODULES
 

Lower LSBs of 1st module can be connect to LSBs of the 2nd module.
You can connect at top level module as per the following -

out(36:28) => E(8:0);
out(27:19) => C(8:0);
out(18:10) => B(8:0);
out(9:0) => A(8:0);

Hope this helps.

~Sachin
 

if you have doubt regarding only inter-connection of module then
this is how i can apply ......

module top_high;
reg Tte_reg;
reg clk_reg;
reg resetn_reg;
wire [35:0]out_wire;

reg [8:0]E_reg;
reg [8:0]A_reg;
reg [8:0]B_reg;
reg [8:0]C_reg;

wire PA_wire,PB_wire,PC_wire;
wire [3:0] chan;

always begin
E_reg = [8:0]out_wire;
A_reg = [17:9]out_wire;
B_reg = [26:18]out_wire;
C_reg = [35:27]out_wire;
end

module top (
.Tte(Tte_reg),
.Clk(clk_reg),
.resetn(resetn_reg),
.out(out_wire)
);

module TopLevel432b (
.E(E_reg),
.A(A_reg),
.B(B_reg),
.C(C_reg),
.PA(PA_wire),
.PB(PB_wire),
.PC(PC_wire),
.Chan(chan_wire)
);
endmodule

this is my basic idea..... please check for any errors
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top